A logical circuit processing a digital signal (hereinafter referred to as a digital circuit) is configured with a single or a plurality of logic elements as a basic unit. The logic element is a circuit which provides one output corresponding to a single input or a plurality of inputs. The logic elements correspond to an inverter, an AND, an OR, a NOT, a NAND, a NOR, a clocked inverter, and a transmission gate (analog switch) and the like, for example.
The logic element is configured with a single circuit element or a plurality of circuit elements such as transistors, resistors and capacitor elements. By operating each of the plurality of circuit elements in accordance with a digital signal inputted to the logic element, a signal potential or a current which is to be supplied to a subsequent circuit is controlled.
Given as an example is an inverter as one of the logic elements. A configuration and operation thereof are explained concretely.
A circuit diagram of a general inverter is shown in FIG. 16. In FIG. 16, IN means an inputted signal (input signal), and OUT means an outputted signal (output signal). Further, VDD and VSS mean power source potentials and VDD>VSS is satisfied.
The inverter shown in FIG. 16 includes a p-channel type TFT 1301 and an n-channel type TFT 1302. A gate (G) of the p-channel type TFT 1301 and a gate of the n-channel type TFT 1302 are connected to each other, and the input signal IN is inputted to these two gates. In addition, VDD is supplied to a first terminal of the p-channel type TFT 1301, and VSS is supplied to a first terminal of the n-channel type TFT 1302. Further, a second terminal of the p-channel type TFT 1301 and a second terminal of the n-channel type TFT 1302 are connected to each other and the output signal OUT is outputted from these two second terminals to a subsequent circuit.
Note that, either of the first terminal or the second terminal corresponds to a source and the other corresponds to a drain. In the case of a p-channel type TFT, a terminal having a higher potential is a source and a terminal having a lower potential is a drain, and in the case of an n-channel type TFT, a terminal having a lower potential is a source and a terminal having a higher potential is a drain. Therefore, the first terminals of the TFTs correspond to sources (S) and the second terminals thereof correspond to drains (D) in FIG. 16.
Generally, for an input signal, a digital signal having binary potentials is utilized. Two circuit elements of the inverter operate in accordance with a potential of the input signal IN, thereby controlling a potential of the output signal OUT.
When VDD or VSS is inputted as the input signal IN, the potential of the output signal OUT becomes VSS or VDD respectively, in which the signal logic is inverted.
Even in the case where VDD′ or VSS′ each having the amplitude larger than the amplitude of the power source voltage is inputted as the input signal IN, each circuit element operates similarly to the case where VDD or VSS is inputted and the potential of the output signal OUT becomes VSS or VDD respectively so that an output signal OUT having a desired potential can be obtained.
In this manner, each circuit element operates in accordance with the potential of the input signal IN generally, thereby controlling the potential of the output signal OUT.
However, in the case where VDD′ or VSS′ each having the amplitude smaller than the amplitude of the power source voltage is inputted as the input signal IN, each circuit element does not operate normally, so that a desired output signal may not be obtained.
Hereinafter verified are operations of an inverter in the case where it is assumed that binary potentials of the input signal IN, VDD′ and VSS′, satisfy VDD′<VDD and VSS′>VSS respectively. Note that VSS′<VDD′ is satisfied.
First, FIG. 16A shows an operating state of each circuit element in the case where the input signal IN has a potential on the high potential side VDD′ (DD′<VDD). Here, it is assumed to simplify the explanation that a threshold voltage VTHn of an n-channel type TFT satisfies VTHn≧0 and a threshold voltage VTHp of a p-channel type TFT satisfies VTHp≦0.
When the potential on the high potential side VDD′ is inputted as the input signal IN, a gate-source voltage VGS of the n-channel type TFT 1302 becomes (VDD′−VSS)>0. (VDD′−VSS) is higher than the threshold voltage VTHn of the n-channel type TFT 1302 generally, thus the n-channel type TFT 1302 is turned ON.
On the other hand, when the potential on the high potential side VDD′ is inputted as the input signal IN, a gate-source voltage VGS of the p-channel type TFT 1301 satisfies (VDD′−VDD)<0. In the case where the gate-source voltage VGS of the p-channel type TFT 1301 is equal to or higher than the threshold voltage VTHp of the p-channel type TFT 1301, the p-channel type TFT 1301 is turned OFF and consequently, a potential VSS supplied to the n-channel type TFT 1302 is outputted so that signal logic is inverted. However, in the case where the gate-source voltage VGS of the p-channel type TFT 1301 is lower than the threshold voltage VTHp of the p-channel type TFT 1301, the p-channel type TFT 1301 is turned ON. Because the gate-source voltage VCS satisfies (VDD′−VDD)<0 and the threshold voltage satisfies VTHp<0, in case that the absolute values of them are compared with each other, when |VGS|≦|VTHp|, the p-channel type TFT 1301 is turned OFF while when |VGS|>|VTHp|, that is |VDD′−VDD|>|VTHp|, the p-channel type TFT 1301 is turned ON.
As mentioned above, when the potential VDD′ is supplied to a gate of the p-channel type TFT 1301, the gate-source voltage satisfies VGS<0 because VDD′<VDD is satisfied. Therefore, when |VGS|>|VTHp|, that is |VDD′−VDD|>|VTHp|, the p-channel type TFT 1301 is turned ON.
Therefore, both the p-channel type TFT 1301 and the n-channel type TFT 1302 are turned ON depending on values of VDD, VDD′, and VTHp. In this case, a potential of an output signal OUT does not become VSS even in the case where an input signal has a potential on the high potential side VDD′.
A potential of the output signal OUT when both the p-channel type TFT 1301 and the n-channel type TFT 1302 are turned ON is determined by the current flowing in each transistor, that is on-resistance (or a source-drain voltage). In FIG. 16A with an input signal of a potential on the high potential side VDD′, when VGS of the n-channel type transistor TFT is referred to as VGSn and VGS of the p-channel type TFT is referred to as VGSp, |VGSn|>|VGSp|. Therefore, the potential of the output signal OUT approaches closer to VSS than VDD when there is almost no difference between transistors as to the characteristics and a ratio of a channel width W to a channel length L. However, the potential of the output signal OUT can approach closer to VDD than VSS depending on the mobility, the threshold voltage, and the ratio of the channel width to the channel length of each TFT. In this case, the digital circuit does not operate normally, leading to a high possibility of malfunction Further, it may cause a sequential malfunction in the subsequent digital circuit.
FIG. 16B shows an operating state of each circuit element in the case where the input signal IN has a potential on the low potential side VSS′ (VSS′>VSS). It is assumed to simplify the explanation that a threshold voltage of the n-channel type TFT VTHn satisfies VTHn≧0 and a threshold voltage of the p-channel type TFT VTHp satisfies VTHp≦0.
When the potential on the low potential side VSS′ is inputted as the input signal IN, a gate-source voltage VGS of the p-channel type TFT 1301 becomes (VSS′−VDD)<0. (VSS′−VDD) is lower than the threshold voltage VTHp of the p-channel type TFT 1301 generally, thus the p-channel type TFT 1301 is turned ON.
On the other hand, when the potential on the low potential side VSS′ is inputted as the input signal IN, a gate-source voltage VGS of the n-channel type TFT 1302 satisfies (VSS′−VSS)>0. In the case where the gate-source voltage VGS of the n-channel type TFT 1302 is equal to or lower than the threshold voltage VTHn of the n-channel type TFT 1302, the n-channel type TFT 1302 is turned OFF. Consequently, a potential VDD supplied to the p-channel type TFT 1301 is outputted, so that signal logic is inverted. However, in the case where the gate-source voltage VGS of the n-channel type TFT 1302 is higher than the threshold voltage VTHn of the n-channel type TFT 1302, the n-channel type TFT 1302 is turned ON. Because the gate-source voltage VGS satisfies (VSS′−VSS)>0 and the threshold voltage satisfies VTHn≧0, in case that the absolute values of them are compared with each other, when |VGS|≦|VTHn|, the n-channel type TFT 1302 is turned OFF while when |VGS|>|VTHn|, that is |VSS′−VSS|>|VTHn|, the n-channel type TFT 1302 is turned ON.
As mentioned above, when the potential VSS′ is supplied to a gate of the n-channel type TFT 1302, the gate-source voltage satisfies VGS>0 because VSS′>VSS is satisfied. Therefore, when |VGS|>|VTHn|, that is |VSS′−VSS|>|VTHn|, the n-channel type TFT 1302 is turned ON.
Therefore, both the p-channel type TFT 1301 and the n-channel type TFT 1302 are turned ON depending on values of VSS, VSS′, and VTHn. In this case, a potential of an output signal OUT does not become VDD even in the case where an input signal has a potential on the low potential side VSS′.
A potential of the output signal OUT when both the p-channel type TFT 1301 and the n-channel type TFT 1302 are turned ON is determined by the current flowing in each transistor, that is on-resistance (or a source-drain voltage). In FIG. 16B with an input signal of a potential on the low potential side VSS′, |VGSn|<|VGSp| is satisfied. Therefore, the potential of the output signal OUT approaches closer to VDD than VSS when there is almost no difference between transistors as to the characteristics and a ratio of a channel width W to a channel length L. However, the potential of the output signal OUT may approach closer to VSS than VDD depending on the mobility, the threshold voltage, and the ratio of the channel width W to the channel length L of each TFT. In this case, the digital circuit does not operate normally, leading to a high possibility of malfunction. Further, it may cause a sequential malfunction in the subsequent digital circuit.
As described above, in the inverters shown in FIG. 16, an output signal OUT having a desired potential is obtained when the binary potentials VDD′ and VSS′ of the input signal IN satisfy that VDD′≧VDD and VSS′≦VSS respectively, thereby a normal operation is obtained. However, when the binary potentials VDD′ and VSS′ of the input signal IN satisfy that VDD′<VDD and VSS′>VSS respectively, the output signal OUT having a desired potential is not obtained, thereby the inverter may not operate normally.
The above is not exclusively limited to the inverter, but can be applied to other digital circuits. That is, when binary potentials of an input signal are out of the predetermined range, the circuit elements of the digital circuit malfunction. Therefore, an output signal OUT having a desired potential can not be obtained and the digital circuit does not function normally.
A potential of the input signal supplied from a circuit of a prior stage or a wiring is not always such a value as to operate the digital circuit normally. In this case, by adjusting the potential of the input signal by a level shifter, the digital circuit can operate normally. However, a high-speed operation of the semiconductor device is frequently hindered by using the level shifter, because level shifters generally have disadvantages in that the speed of rising and falling of the potential of the output signal is slow as each of the circuit elements operates in conjunction such that an operation of one circuit element triggers the operations of other circuit elements.
In addition, the problem of increasing current consumption arises since the n-channel type TFT 1302 and the p-channel type TFT 1301 are simultaneously turned ON to flow a penetrating current.
In view of the above-described problems, it is an object of the present invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. In more detail it is an object to provide a digital circuit which can operate normally even in the case where the amplitude of an input signal is smaller than the amplitude of a power source voltage.